The present disclosure relates to a method for producing chip stacks and to associated chip stacks, and in particular to a method for producing ultrathin chip stacks having a total thickness of less than 500 μm.
In order to reduce costs or in order to realize highly complex semiconductor circuits, use is increasingly being made of so-called chip stacks, two semiconductor components provided with semiconductor circuits, or so-called chips being connected to one another by means of e.g. the so-called face-to-face (F2F) or SOLID method. To put it more precisely, in this case a first partial semiconductor circuit may be formed in one semiconductor component or semiconductor chip and a second partial semiconductor circuit may be realized in a second semiconductor component or semiconductor chip, which partial semiconductor circuits enable an overall functionality when connected up together.
In this case, either analog or radio frequency circuits or memory modules of digital semiconductor circuits may be separated locally or in particular semiconductor partial circuits, which require a cost-intensive processing, of semiconductor circuits which enable a cost-effective realization may subsequently be combined, whereby the production costs can be reduced to a remarkable extent.
In the case of the face-to-face or SOLID methods such as are disclosed for example in the documents WO20041086497 and WO2004/068573 for the so-called 3D mounting or vertical processing of semiconductor components or semiconductor chips on a processed wafer with still unsingulated semiconductor chips, singulated semiconductor chips are soldered “face-down”, that is to say with their processed surface onto a processed wafer. This is done using F2F pads (Face-to-Face) and F2F metal tracks which are approximately 15×15 μm size and are embodied for example from thick Cu layers in the lower wafer and as a thick Cu layer with an overlying Sn layer on the semiconductor chips to be mounted. Metal tracks or pads of this type are referred to hereinafter as chip connection areas.
After alignment of the semiconductor chip to be mounted above the associated chip connection areas (F2F pads and F2F metal tracks) of the further semiconductor chips formed in the wafer, the structures are soldered e.g. under protective gas atmosphere and at temperatures of approximately 300 degrees Celsius. In this case, an intermetallic Cu3Sn phase is formed as an electrically conductive connecting layer, which is stable up to 600 degrees Celsius after its shaping. A method for producing such a soldering connection or electrically conductive connecting layer is disclosed for example in the document WO02/20211A1.
Conventional semiconductor wafers have a thickness of approximately 700 μm, for which reason thicknesses of greater than 1400 μm arise for a resulting chip stack. However, a total thickness of less than 500 μm is required for a multiplicity of present-day and future applications in electronic components, and in particular of integrated circuits. Such thin semiconductor circuits or chip stacks have a very small mass and a very small structural height, for which reason they are of importance for a multiplicity of fields of application, for example in future disposable electronics and also for chip cards and smart cards.
For chip card applications, in particular, a total thickness of the ultrathin chip stacks should be less than 300 μm. However, as soon as such thin semiconductor chips having a thickness of less than 200 μm are mounted by means of an F2F method (Face-to-Face), alignment and adhesion problems are manifested particularly during soldering. The cause of these problems resides in the flexure of the thinned semiconductor chips which occurs on account of the intrinsic mechanical stress in the semiconductor chip.
On the other hand, however, it is also not possible for the singulated semiconductor chips that have already been soldered onto the semiconductor wafer simply to be thinned by grounding, since the soldering connections or the electrically conductive connecting layer is mechanically loaded to an excessively great extent and impermissibly degraded by the shearing forces that occur in the course of thinning by grounding. This results in problems with regard to the reliability and yield. On the other hand, wet-chemical etching methods are likewise not possible since both the singulated semiconductor chips and the unsingulated semiconductor chips which, however, are still situated in the wafer have already been completely processed and would accordingly be damaged.